High-Performance Ternary Adder Using CNTFET-Reference-Cited by-同舟云学术

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High-Performance Ternary Adder Using CNTFET

Published:2017-05 Issue:3 Volume:16 Page:368-374
ISSN:1536-125X
Container-title:IEEE Transactions on Nanotechnology
language:
Short-container-title:IEEE Trans. Nanotechnology

Author:

Sahoo Subhendu Kumar,Akhilesh Gangishetty,Sahoo Rasmita,Muglikar Manasi

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Science Applications

Link

http://xplorestaging.ieee.org/ielx7/7729/7927511/07809029.pdf?arnumber=7809029

Cited by 76 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Energy-Efficient Exact and Approximate CNTFET-Based Ternary Full Adders;Circuits, Systems, and Signal Processing;2024-01-29

2. CNTFET-based Approximate Ternary Adder Design;2023 30th IEEE International Conference on Electronics, Circuits and Systems (ICECS);2023-12-04

3. T³L: A Practical Implementation of Tri-Transistor Ternary Logic Based on Inkjet-Printed Anti-Ambipolar Transistors and CMOSs of Thin-Film Structure;IEEE Transactions on Circuits and Systems I: Regular Papers;2023-12

4. Design of ternary full-adder and full-subtractor using pseudo NCNTFETs;e-Prime - Advances in Electrical Engineering, Electronics and Energy;2023-12

5. Design of Binary and Ternary Logic Inverters Based on Silicon Feedback FETs Using TCAD Simulator;IET Circuits, Devices & Systems;2023-10-23

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