Proposed Pipeline Clocking Scheme for Microarchitecture Data Propagation Delay Minimization
Author:
Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-15-3828-5_8
Reference23 articles.
1. Sung RJH et al (2007) Clock-logic domino circuits for high-speed and energy efficient microprocessor pipelines. IEEE Trans Circ Syst-II: Express Briefs 54(5):460–464
2. Yang S et al (2007) Surfing pipelines: theory and implementation. IEEE J Solid-State Circ 42(6):1405–1414
3. Lee H et al (2010) Pulse width allocation and clock skew scheduling: Optimization sequential circuits based on pulsed latches. IEEE Trans Comput Aided Des Integr Circ Syst 29(3)
4. Rantala A et al (2007) A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 µm CMOS. Springer Science, analog integrated circuit signal process, pp 69–79
5. Han Kihyuk et al (2011) Off-chip skew measurement and compensation module (SMCM) design for built-off test chip. Springer J Electron Test 27:429–439
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