A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS-Reference-Cited by-同舟云学术

A DLL clock generator for a high speed A/D-converter with 1 ps jitter and skew calibrator with 1 ps precision in 0.35 μm CMOS

Published:2007-01 Issue:1 Volume:50 Page:69-79
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Rantala Arto,Martins David Gomes,Åberg Markku

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-006-9398-5.pdf

Reference10 articles.

1. A. Rantala, D. Gomes Martins, and M. Åberg, “A DLL based clock generator for a high-speed time-interleaved A/D-converter.” In Proceeding of the IEEE Norchip 2003 Conference, Riga, Latvia, Nov. 2003.

2. K. Poulton, R. Neff, A. Muto, L. Wei, A. Burstein, and M. Heshami, “A 4 Gsample/s 8b ADC in 0.35 μm CMOS.” Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. IEEE International, vol. 1, no. 20, pp. 166–457, 2002.

3. K. Poulton, R. Neff, B. Setterberg, B. Wuppermann, T. Kopley, R. Jewett, J. Pernillo, C. Tan, and A. Monntijo, “A 20 GS/s 8b ADC with a 1 MB Memory in 0.18 μm CMOS.” Solid-State Circuits Conference. 2003. Digest of Technical Papers. ISSCC. 2003 IEEE International, pp. 318–319.

4. R. Farjad-Rad, W. Dally, H.-T. Ng, R. Senthinathan, M.-J.E. Lee, R. Rathi, and J. Poulton, “A low-power multiplying DLL for low-jitter multigigahertz clock generation in highly integrated digital chips.” IEEE Journal of Solid-State Circuits, vol. 37, no. 12, pp. 1804–1812, 2002.

5. http://www.icst.com/products/datasheets/m650.pdf

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