Design of a Virtual Channel Router Architecture for Low Power on Mesh-of-Grid Topology for Network on Chip-Reference-Cited by-同舟云学术

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Design of a Virtual Channel Router Architecture for Low Power on Mesh-of-Grid Topology for Network on Chip

Published:2020 Issue: Volume: Page:63-79
ISSN:2367-3370
Container-title:Applied Soft Computing and Communication Networks
language:
Short-container-title:

Author:

Somasundaram K.

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-15-3852-0_5

Reference32 articles.

1. De Micheli G, Benini L (2006) Networks-on-chip: technology and tools. Elsevier

2. Flich J, Bertozzi D (2010) Designing network-on-chip architectures in the nanoscale era. Chapman & Hall/CRC

3. Kundu S, Chattopadhyay S (2018) Network-on-chip: the next generation of system-on-chip integration. CRC Press

4. Ogras UY, Marculescu R (2013) Modeling, analysis and optimization of network-on-chip communication architectures. Lecture notes in electrical engineering, vol 184. Springer. https://doi.org/10.1007/978-94-007-3958-i

5. Sahu PK, Chattopadhyay S (2013) A survey on application mapping strategies for network-on-chip design. J Syst Architect 59(1):60–76. https://doi.org/10.1016/j.sysarc.2012.10.004

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1. Cycle-accurate multi-FPGA platform for accelerated emulation of large on-chip networks;The Journal of Supercomputing;2024-06-23

2. Low power NoC buffer protection using error correction code;SECOND INTERNATIONAL CONFERENCE ON CIRCUITS, SIGNALS, SYSTEMS AND SECURITIES (ICCSSS - 2022);2023

3. Congestion Aware Negative First Routing with Fair Arbitration for Network on Chip;2022 6th International Conference on Computing Methodologies and Communication (ICCMC);2022-03-29

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