Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder
Author:
Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-10-7470-7_4
Reference11 articles.
1. Barakat, M., Saad, W., Shokair, M., Elkordy, M.: Implementation of efficient portable low delay adder using FPGA. In: 28th International Conference on Microelectronics ICM (2016)
2. Suganya, R., Meganathan, D.: High performance VLSI adders. In: 3rd International Conference on Signal Processing, Communication and Networking ICSCN (2015)
3. Katz, R.H.: Contemporary Logic Design. Benjamin Publishing Co., CA (1994)
4. Ling, H.: High-speed binary adder. IBM J. Res. Dev. 25, 156–166 (1981)
5. Saji Antony, M., Sri Ranjani Prasanthi, S., Indu, S., Pandey, R.: Design of high speed Vedic multiplier using multiplexer based adder. In: International Conference on Control Communication & Computing India ICCC (2015)
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