1. Design and Comparison of 24-bit Three Operand Adders using Parallel Prefix method for Efficient Computations;ICST Transactions on Scalable Information Systems;2024-02-01
2. Cryogenic CMOS as an Enabler for Low Power Dynamic Logic;2023 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED);2023-08-07
3. A Variable Latency Ling Adder Based on Brent-Kung Parallel-Prefix Topology;2023 IEEE 23rd International Conference on Nanotechnology (NANO);2023-07-02
4. Design and Analysis of Three Operand Binary Adder;2023 Second International Conference on Electrical, Electronics, Information and Communication Technologies (ICEEICT);2023-04-05
5. T-PIM: An Energy-Efficient Processing-in-Memory Accelerator for End-to-End On-Device Training;IEEE Journal of Solid-State Circuits;2023-03