Implementation of efficient portable low delay adder using FPGA-Reference-Cited by-同舟云学术

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Implementation of efficient portable low delay adder using FPGA

Published:2016-12 Issue: Volume: Page:
ISSN:
Container-title:2016 28th International Conference on Microelectronics (ICM)
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Author:

Barakat Mohamed,Saad Waleed,Shokair Mona,Elkordy Mohamed

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/7835397/7847841/07847859.pdf?arnumber=7847859

Cited by 2 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Efficiency Analysis of Adder Architectures: A Comparative Study Across Various Bit Lengths;2024 IEEE International Conference on Information Technology, Electronics and Intelligent Communication Systems (ICITEICS);2024-06-28

2. Realization of Multiplier Using Delay Efficient Cyclic Redundant Adder;Communications in Computer and Information Science;2017

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