MBFF for Power Reduction of an SoC Partition-Reference-Cited by-同舟云学术

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MBFF for Power Reduction of an SoC Partition

Published:2020-09-20 Issue: Volume: Page:911-919
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
Short-container-title:

Author:

Anandi V.,Shanmathi G.,Ramesh Muthuswamy

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-15-5546-6_75

Reference15 articles.

1. Shinde J, Salankar SS (2011) Clock gating—a power optimizing technique for VLSI circuits. In: Annual IEEE India conference, https://doi.org/10.1109/indcon.2011.6139440 , 16–18 December 2011

2. Madhushree, Rajan N (2017) Dynamic power optimization using look-ahead clock gating technique. In: 2nd IEEE international conference on recent trends in electronics information & communication technology (RTEICT), India, 19–20 May 2017

3. Chakraverty M, Harisankar PS, Ruparelia V (2016) Low power design practices for power optimization at the logic and architecture levels for VLSI system design. In: 2016 International conference on energy efficient technologies for sustainability (ICEETS), IEEE, 6th October 2016, pp 727–733

4. Hsu C-C, Chen Y-C, Lin MP-H (2015) In-placement clock-tree aware multi-bit flip-flop generation for power optimization. IEEE Trans Comput-Aided Des Integr Circ Syst 34(2)

5. Cherif L, Chentouf M, Benallal J, Darmi M, Elgouri R, Hmina N (2018) Usage and impact of multi-bit flip-flops low power methodology on physical implementation. In: 4th International conference on optimization and applications (ICOA). https://doi.org/10.1109/icoa.2018.8370498 , 26–27 April 2018

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