1. Xue F, Jiang A, Zhao H, Chen YT, Wang Y, Zhou F, Lee J (2012) Sub-50-nm In0.7Ga0.3As MOSFETs with various barrier layer materials. IEEE Electron Device Lett 33(1):32–34
2. Lin D, Brammertz G, Sioncke S, Fleischmann C, Delabie A, Martens K, Bender H, Conard T, Tseng WH, Lin JC, Wang WH, Temst K, Vatomme A, Mitard J, Caymax M, Meuris M, Heyns M, Hoffmann T (2009) Enabling the high-performance InGaAs/Ge CMOS: a common gate stack solution. In: Proceedings of international electron devices meeting, pp 327–330
3. Takagi S, Yokoyama M, Kim S-H, Zhang R, Suzuki R, Taoka N, Takenaka M (2013) III-V/Ge CMOS device technologies for high performance logic applications. ECS Trans 53(3):85–96
4. Irisawa T, Oda M, Kamimuta Y, Moriyama Y, Ikeda K, Mieda E, Jevasuwan W, Maeda T, Ichikawa O, Osada T, Hata M, Tezuka T (2013) Demonstration of InGaAs/Ge dual channel CMOS inverters with high electron and hole mobility using stacked 3D integration. In: Symposium on VLSI technology digest of technical papers, pp T56–T57
5. De S, Tewari S, Biswas A, Mallik A (2017) Impact of channel thickness and spacer length on logic performance of p-Ge/n-Si hybrid CMOSFETs for ULSI applications. Superlattices Microstruct 109:316–323