1. Sub-50-nm In0.7Ga0.3As MOSFETs with various barrier layer materials;Xue;IEEE Electron Device Lett.,2012
2. Ënabling the high-performance InGaAs/Ge CMOS: a common gate stack solution;Lin,2009
3. Investigation on high performance CMOS with p-Ge and n-InGaAs MOSFETs for logic applications;Tewari;IEEE Trans. Nanotechnol.,2015
4. III-V/Ge CMOS device technologies for high performance logic applications;Takagi;ECS Trans.,2013
5. T. Irisawa, M. Oda, Y. Kamimuta, Y. Moriyama, K. Ikeda, E. Mieda, W. Jevasuwan, T. Maeda, O. Ichikawa, T. Osada, M. Hata and T. Tezuka, Demonstration of InGaAs/Ge dual channel CMOS inverters with high electron and hole mobility using stacked 3D integration, Symposium on VLSI Technology Digest of Technical Papers, (2013) T56–T57.