Optimized FPGA Implementation of 64-Point FFT Using Folding Transformation
Author:
Nafzia ,Lijesh L.
Publisher
Springer Singapore
Reference21 articles.
1. P. Zode, A.Y. Deshmukh, An area efficient FFT structures design by sharing arithmetic units. IOSR J. VLSI Sig. Process. (IOSR-JVSP) 7(3), 01–07 (2017)
2. Z. Ma, X. Yin, F. Yu, A novel memory-based FFT architecture for real-valued signals based on radix-2 decimation-in-frequency algorithm. IEEE Trans. Circ. Syst. II Express Briefs 62(9) (2015)
3. S. He, M. Torkelson, Designing pipeline FFT processor for OFDM (de)modulation, in Signals, Systems, and Electronics, Sweden (1998)
4. A. Singhal, A. Goen, T.T. Mohapatrara, Design and implementation of fast Fourier transform (FFT) using VHDL code. Int. J. Emerg. Res. Manag. Technol. 6(8) (2017)
5. M. Ayinala, K.K. Parhi, Parallel–pipelined radix-22 FFT architecture for real valued signals. IEEE, USA (2010)