Parallel - pipelined radix-2<sup>2</sup> FFT architecture for real valued signals-Reference-Cited by-同舟云学术

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Parallel - pipelined radix-2² FFT architecture for real valued signals

Published:2010-11 Issue: Volume: Page:
ISSN:
Container-title:2010 Conference Record of the Forty Fourth Asilomar Conference on Signals, Systems and Computers
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Author:

Ayinala Manohar,Parhi Keshab K.

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx5/5752164/5757211/05757736.pdf?arnumber=5757736

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Optimized FPGA Implementation of 64-Point FFT Using Folding Transformation;Lecture Notes in Electrical Engineering;2021-12-14

2. Area-Efficient Pipelined FFT Processor for Zero-Padded Signals;Electronics;2019-11-22

3. A Continuous-Flow Memory-Based Architecture for Real-Valued FFT;IEEE Transactions on Circuits and Systems II: Express Briefs;2017-11

4. Resource-Efficient Pipelined Architectures for Radix-2 Real-Valued FFT With Real Datapaths;IEEE Transactions on Circuits and Systems II: Express Briefs;2016-08

5. A Novel Memory-Based FFT Architecture for Real-Valued Signals Based on a Radix-2 Decimation-In-Frequency Algorithm;IEEE Transactions on Circuits and Systems II: Express Briefs;2015-09

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