Performance Analysis of 3-D Parallel Gated Junctionless Field Effect Nanowire Transistor
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-0252-9_26
Reference16 articles.
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3. Colinge JP, Lee CW, Afzalian A, Akhavan ND, Yan R, Ferain I, Razavi P, O’Neill B, Blake A, White M, Kelleher AM, McCarthy B, Murphy R (2010) Nanowire transistors without junctions. Nat Nanotechnol 5:225–229. https://doi.org/10.1038/nnano.2010.15
4. Bora N, Das P, Subadar R (2003) An analytical universal model for symmetric double gate junctionless transistors. J Nano Electron Phys 8. https://doi.org/10.21272/jnep.8(2).02003
5. Bora N, Subadar R (2019) A complete analytical model of surface potential and drain current for an ultra short channel double gate asymmetric junctionless transistor. J Nanoelectron Optoelectron 14:1283–1289. https://doi.org/10.1166/jno.2019.2643
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