Core Performance Based Packet Priority Router for NoC-Based Heterogeneous Multicore Processor-Reference-Cited by-同舟云学术

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Core Performance Based Packet Priority Router for NoC-Based Heterogeneous Multicore Processor

Published:2020-08-11 Issue: Volume: Page:389-397
ISSN:2194-5357
Container-title:Advances in Intelligent Systems and Computing
language:
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Author:

Indragandhi K.,Jawahar P. K.

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-15-5400-1_40

Reference11 articles.

1. Dally, W., & Towles, B. (2004). Principles and practices of interconnection networks. San Francisco: Morgan Kaufmann Pub.

2. Saponara, S., & Fanucci, L. (2012). Homogeneous and heterogeneous MPSoC architectures with network-on-chip connectivity for low-power and real-time multimedia signal processing. Hindawi Publishing Corporation, VLSI Design.

3. Swapna, S., Swain, A., & Mahapatra, K. (2012). Design and analysis of five port router for network on chip, 51–55. https://doi.org/10.1109/primeasia.2012.6458626 .

4. George, M., Alagarsamy, A., & Lakshminarayanan, G. (2017). Design of five port priority based router with port selection logic for NoC. ICTACT Journal on Microelectronics, 02, 293–299. https://doi.org/10.21917/ijme.2017.0051 .

5. Zhou, X., Zhu, Z., & Zhou, D. (2016). A load balancing bufferless deflection router for network-on-chip. Journal of Semiconductors, 37(7).

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1. FPGA based Design and Simulation of basic Routing Protocols;2022 Fourth International Conference on Cognitive Computing and Information Processing (CCIP);2022-12-23

2. TB-NUCA: A Temperature-Balanced 3D NUCA Based on Bayesian Optimization;Electronics;2022-09-14

3. Thermal-aware routing algorithm in partially connected 3D NoC with dynamic availability for elevators;Journal of Ambient Intelligence and Humanized Computing;2022-08-03

4. Two-step thermal-aware routing algorithm in 3D NoC;2021 11th International Conference on Computer Engineering and Knowledge (ICCKE);2021-10-28

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