Cache Memory Architecture for Core Processor
Author:
Publisher
Springer Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-16-5207-3_66
Reference23 articles.
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2. Fragasse, R., et al.: Analysis of SRAM enhancements through sense amplifier capacitive offset correction and replica self-timing. IEEE Trans. Circuits Syst. I Regul. Pap. 66(6), 2037–2050 (2019)
3. Tripti, T., Chauhan, D.S., Singh, S.K., Singh, S.V.: Implementation of low-power 6T SRAM cell using MTCMOS technique. In: Advances in Computer and Computational Sciences. Springer, Singapore (2017)
4. Geetha Priya, M., Baskaran, K., Krishnaveni, D.: Leakage power reduction techniques in deep submicron technologies for VLSI applications. ELSEVIER, International Conference on Communication Technology and System Design (2011)
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