Author:
Kaibartta Tanusree,Das Debesh Kumar
Reference9 articles.
1. IEEE Std.1500: IEEE Standard Testability Method for Embedded Core based Integrated Circuits. IEEE, New York (2005)
2. Puttuswamy, K., Loh, G.H.: The impact of 3-dimensional integration on the design of arithmetic units. In: IEEE International Symposium on Circuits and Systems, pp. 4951–4954. IEEE, Greece (2006)
3. Iyengar, V., Chakrabarty, K., Marinissen, E.J.: Test wrapper and test access mechanism co-optimization for system-on-chip. J. Electron. Test. Theory Appl. 18, 213–230 (2002)
4. Goel, S.K., Marinissen, E.J.: SOC test architecture design for efficient utilization of test bandwidth. ACM Trans. Des. Autom. Electron. Syst. 8(4), 399–429 (2003)
5. Giri, C., Sarkar, S., Chattopadhyaya, S.: A genetic algorithm based heuristic technique for power constrained test scheduling in core-based SOCs. In: IEEE Proceedings of IFIP International Conference on Very Large Scale Integration, USA, pp. 320–323 (2007)
Cited by
1 articles.
订阅此论文施引文献
订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献