Design of Speed and Area Efficient Non Linear Carry Select Adder (NLCSLA) Architecture Using XOR Less Adder Module

Author:

Ykuntam Yamini Devi,Penumutchi Bujjibabu,Gubbala Srilakshmi

Publisher

Springer Nature Singapore

Reference16 articles.

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2. SaiKumar M, Samundiswary DP (2013) Design and performance analysis of various adders using verilog. Int J Comput Sci Mob Comput 2(9):128–138

3. Jayanthi AN, Ravichandran CS (2013) Comparison of performance of high speed VLSI adders. In: 2013 international conference on current trends in engineering and technology (ICCTET). IEEE, pp 99–104

4. Ramkumar B, Kittur HM, Kannan PM (2010) ASIC implementation of modified faster carry save adder. Eur J Sci Res 42(1):53–58

5. Kavya KVSSSS, Penumutchi B, Nandan D (2021) Analysis on high-performance full adders. In: Next Generation Information Processing System. Springer, Singapore, pp 122–131

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