Modeling and Performance Analysis of n-FinFETs: A Comparative Study
Author:
Jena J.ORCID, Dash T. P., Mohapatra E., Das S., Nanda J., Maiti C. K.
Publisher
Springer Singapore
Reference15 articles.
1. Dash, T.P., Dey, S., Das, S., Jena, J., Mohapatra, E., Maiti, C.K.: Performance Comparison of strained-SiGe and bulk-Si channel FinFETs at 7 N technology node. J. Micromech. Microeng. 29, 104001 (2019) 2. Jena, J., Dash, T.P., Mohapatra, E., Dey, S., Das, S., Maiti, C.K.: Fin shape dependence of electrostatics and variability in FinFETs. J. Electron. Mater. 48, 6742–6752 (2019) 3. Dash, T.P., Dey, S., Das, S., Jena, J., Mohapatra, E., Maiti, C.K.: Source/drain stressor design for advanced devices at 7 nm technology nodes. Nanosci. Nanotech. Asia (2019) 4. Choi, Y.-K., Chang, L., Ranade, P., Lee, J.S., Ha, D., Balasubramanian, S., Agarwal, A., Ameen, M., King, T.J., Bokor, J.: FinFET process refinements for improved mobility and gate work function engineering. In: Proceedings of IEDM, pp. 259–262 (2002) 5. Huajie, Z., Yi, S., Qiuxia, X., Yongliang, L., Huaxiang, Y.: Fabrication of Bulk-Si FinFET using CMOS compatible process. Microelectron. Eng. 94, 26–28 (2012)
|
|