Butterfly-Fat-Tree Topology-Based Fault-Tolerant Network-on-Chip Design Using Particle Swarm Optimization
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-13-0761-4_108
Reference16 articles.
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2. Benini, L., De, Micheli G.: Networks on chips: a new SoC paradigm. IEEE. Comput. 35(1), 70–78 (2002)
3. Dally, W., Towles, B.: Route packets, not wires: on-chip interconnection networks. In: Proceedings of the 38th Design Automation Conference (IEEE Cat. No. 01CH37232) DAC 2001, pp. 684–689. Las Vegas, Nevada, USA (2001)
4. Soumya, J., Chattopadhyay, S.: Application-specific network-on-chip synthesis with flexible router placement. J. Syst. Archit. 59(7), 361–371 (2013)
5. Radetzki, M., Feng, C., Zhao, X., Jantsch, A.: Methods for fault tolerance in networks-on-chip. ACM Comput. Surv. 46(1), 8 (2013)
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