Leakage Power Reduction in CMOS Inverter at 16 nm Technology
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-99-4634-1_62
Reference22 articles.
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2. Naffziger S et al (2021) Pioneering chiplet technology and design for the AMD EPYCTM and RyzenTM processor families: industrial product in proceedings—international symposium on computer architecture, 2021. https://doi.org/10.1109/ISCA52012.2021.00014
3. Pal S, Arif S (2015) A fully differential read-decoupled 7-T SRAM cell to reduce dynamic power consumption. ARPN J Eng Appl Sci 10(5):2142–2147
4. Roy C, Islam A. Design of low power, variation tolerant single bit line 9T SRAM cell in 16-nm technology in subthreshold region. Microelectron Reliab. https://doi.org/10.1016/j.microrel.2021.114126
5. Dadori AK, Khare K, Gupta TK, Singh RP (2017) Leakage power reduction technique by using multigate FinFET in DSM technology. Advan Intel Syst Comput. https://doi.org/10.1007/978-981-10-2750-5_25
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