FPGA-Masked S-Box Implementation for AES Engine-Reference-Cited by-同舟云学术

FPGA-Masked S-Box Implementation for AES Engine

Published:2018 Issue: Volume: Page:223-233
ISSN:1876-1100
Container-title:Lecture Notes in Electrical Engineering
language:
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Author:

Jayakumar Maneesha

Publisher

Springer Singapore

Link

http://link.springer.com/content/pdf/10.1007/978-981-10-7251-2_24

Reference8 articles.

1. Zhang X, Parhi KK (2002) Implementation approaches for the advanced encryption standard algorithm. IEEE Circuits Syst Mag 2(4):24–46

2. Jing MH, Chen YH, Chang YT, Hsu CH (2001) The design of a fast inverse module in AES. In: Proceedings of the International Conference on Info-Tech and Info-Net, vol 3, Beijing, China, Nov 2001, pp 298–303

3. Satoh A, Morioka S, Takano K, Munetoh S (2000) A compact Rijndael hardware architecture with S-box Optimization. In: Proceedings of the ASIACRYPT 2001, Gold Coast, Australia, Dec 2000, pp 239–254

4. Rudra A, Dubey PK, Jutla CS, Kumar V, Rao JR, Rohatgi P (2001) Efficient implementation of Rijndael encryption with composite field arithmetic. In: Proceedings of the CHES 2001, Paris, France, May 2001, pp 171–184

5. Kuo H, Verbauwhede I (2001) Architectural optimization for a 1.82 Gbits/sec VLSI implementation of the AES Rijndael algorithm. In: Proceedings of the 2001, Paris, France, May 2001, pp 51–64

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