Power profiling-based side-channel attacks on FPGA and Countermeasures: A survey
Author:
Affiliation:
1. College of EME, NUST,Department of Computer and Software Engineering,Islamabad,Pakistan
Publisher
IEEE
Link
http://xplorestaging.ieee.org/ielx7/9787390/9787393/09787473.pdf?arnumber=9787473
Reference42 articles.
1. Multiplicative Masking for AES in Hardware
2. FPGA-Masked S-Box Implementation for AES Engine
3. Remote inter-chip power analysis side-channel attacks at board-level
4. Differential Power Analysis
5. FPGA-Based Obfuscated Delay PUF for Security Enhancement Against ML-Attack
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1. Role of Machine Learning in Power Analysis Based Side Channel Attacks on FPGA;2023 International Conference on Robotics and Automation in Industry (ICRAI);2023-03-03
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