Efficient Implementation of Carry-Skip Adder Using CSMT Adder and PPA
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-13-7166-0_29
Reference10 articles.
1. Ramkumar, B., Kittur, H.M.: Low-power and area-efficient carry select adder. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 20(2) (Feb 2012)
2. Kumar, A., Singh, A.S.: Full adder using multiplexer. IJIRT 1(12) (2015)
3. Nagendra, A., Irwin, M.J., Owens, R.M.: Area-time-power tradeoffs in parallel adders. IEEE Trans. Circuits Syst. II 43, 689–702 (1996)
4. Chirca, K., Schulte, M., Glossner, J.: A static low-power, high-performance 32-bit carry skip adder. In: IEEE Conference on Digital System Design (2004)
5. Parhi, K.K., Low-energy CSMT carry generators and binary adders. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 7(4) (Dec 1999)
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1. A delay efficient hybrid parallel prefix variable latency CSKA based multi-operand adder with optimized 5:2 compressor and skip logic;International Journal of Electronics;2022-06-13
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