Author:
Machupalli Madhusudhan Reddy,Krishnaveni Challa ,Bathula Murali Krishna,Rajesh Kumar G.,Posupo Raja
Publisher
Springer Nature Singapore
Reference8 articles.
1. Sorwar, A., Rangon, M.M.T., Sojib, E.A., Chowdhury, M.S.A., Dipto, M.A.Z., Siddique, A.H.: Design of a high-performance 2-bit magnitude comparator using hybrid logic style. 11th ICCCNT 2020—IIT, Kharagpur, pp. 1–6. IEEE Xplore, India (2020)
2. Mukherjee, D.N., Panda, S., Maji, B.: Performance evaluation of digital comparator using different logic styles. IETE J. Res. 64, 422–429 (2018)
3. Kang, S., Leblebici, Y.: CMOS digital integrated circuit, analysis and design, 3rd edn., pp. 295–302. Tata McGrawHill, New Delhi (2003)
4. Sharma, A., Singh, R., Kajla, P.: Area efficient 1-bit comparator design by using hybridized full adder module based on PTL and GDI logic. Int. J. Comput. Appl. 82, 5–13 (2013)
5. Kumar, D., Kumar, M.: Design of low power two-bit magnitude comparator using adiabatic logic. In: 2016 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS), pp. 1–6. IEEE Xplore, Thailand (2017)
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