FPGA Implementation of 16-Bit Wallace Multiplier Using HCA

Author:

Ram G. Challa,Subbarao M. Venkata,Kumar D. Girish,Terlapu Sudheer Kumar

Publisher

Springer Nature Singapore

Cited by 3 articles. 订阅此论文施引文献 订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献

1. LUT-Based Area-Optimized Accurate Multiplier Design for Signal Processing Applications;Lecture Notes of the Institute for Computer Sciences, Social Informatics and Telecommunications Engineering;2024

2. Area Optimised Efficient Multiplication Using Modified Round Square Approximation;2023 IEEE International Conference on Integrated Circuits and Communication Systems (ICICACS);2023-02-24

3. Delay Enhancement of Wallace Tree Multiplier with Binary to Excess-1 Converter;2023 5th International Conference on Smart Systems and Inventive Technology (ICSSIT);2023-01-23

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