Area Optimised Efficient Multiplication Using Modified Round Square Approximation-Reference-Cited by-同舟云学术

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Area Optimised Efficient Multiplication Using Modified Round Square Approximation

Published:2023-02-24 Issue: Volume: Page:
ISSN:
Container-title:2023 IEEE International Conference on Integrated Circuits and Communication Systems (ICICACS)
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Author:

Raju G.R.L.V.N. Srinivasa¹,Nikitha Thota Nirmal¹,Ram G. Challa¹,Chary Udari Gnaneshwara²,Vardhan J. Naga Vishnu³,Kumar J. Doondi⁴

Affiliation:

1. Shri Vishnu Engineering College for Women,Department of ECE,Bhimavaram,India

2. B V Raju Institute of Technology,Department of ECE,Narsapur,India

3. BVRIT Hyderabad College of Engineering for Women,Department of ECE,Hyderabad,India

4. Vishnu Institute of Technology,Department of ECE,Bhimavaram,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10099473/10099480/10099920.pdf?arnumber=10099920

Reference15 articles.

1. Energy-efficient high-speed CMOS pipelined multiplier

2. A 1.8V 1.1GHz novel digital multiplier

3. Design and Evaluation of Approximate Logarithmic Multipliers for Low Power Error-Tolerant Applications

4. Approximate Multiplier Architectures for Error Resilient Applications

5. Modified Booth multipliers with a regular partial product array;kuang;IEEE Transactions OnCircuits and Systems I,2009

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