Development of Flip Chip Bonding Process on Silicon Interposer by Using Copper Pillar
Author:
Publisher
Springer Nature Singapore
Link
https://link.springer.com/content/pdf/10.1007/978-981-19-1309-9_66
Reference8 articles.
1. Iyer, S.S., Kirihata, T.: Three-dimensional integration, a tutorial for designers. IEEE Solid State Circuits Mag. 7(4), 63–74 (2015)
2. Massa, S., Shahin, D., Wathuthanthri, I., Drechsler, A., et al.: Process development for flip chip bonding with different bump compositions. In: 2019 International Wafer Level Packaging Conference (IWLPC), San Jose, CA, USA, pp. 1–6 (2019)
3. Tsao, P.H., Hsu, S., Kuo, Y.L., Chen, J.H., et al.: Cu bump flip chip package reliability on 28nm technology. In: 2016 IEEE 66th Electronic Components and Technology Conference (ECTC), Las Vegas, NV, USA, pp. 1148–1153 (2016)
4. Inoue, F., Derakhshandeh, J., Lofrano, M., Beyne, E.: Fine-pitch bonding technology with surface-planarized solder micro-bump/polymer hybrid for 3D integration. Jpn. J. Appl. Phys. 60(2), 026502 (2021)
5. Bajwa, A.A., Jangam, S.C., Pal, S., Marathe, N., et al.: Heterogeneous integration at fine pitch (≤10µm) using thermal compression bonding. In: 2017 IEEE 67th Electronic Components and Technology Conference, Orlando, FL, USA, pp. 1276–1284 (2017)
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