Design of Low Power and High-Speed CMOS Phase Frequency Detector for a PLL
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Publisher
Springer Singapore
Link
http://link.springer.com/content/pdf/10.1007/978-981-13-2553-3_51
Reference13 articles.
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3. Soliman, S., Yuan, F., Raahemifar, K.: An overview of design techniques for CMOS phase detector. In: Proceedings of IEEE International symposium on circuits and systems, pp. V-457–V-460, Phoenix Scottsdale, AZ, USA (2002)
4. Nikolic, G., Jovanovic, G., Stojcev, M., Nikolic, T.: Precharge phase detector with zero dead zone and minimal blind-zone. J. Circuits Syst. Comput. 26(11), 1750179-1–1750179-15 (2017)
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1. A High Speed Phase Detection Circuit with No Dead Zone Suitable for Minimal Jitter and Low Power Applications;Journal of Circuits, Systems and Computers;2022-06-22
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3. An Efficient Implementation of an Effective PFD-CP for Low Power Low-Jitter CP-PLL;Lecture Notes in Electrical Engineering;2021-07-22
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