1. Gupta RK, Rathi M (2017) Comparison of various leakage power reduction techniques for full adder circuit
2. Kang S, Leblibici Y (2013) CMOS digital integrated circuits: analysis and design. Tata McGraw Hill
3. Yeo K-S, Roy K (2004) Low-voltage, low-power VLSI subsystems. McGraw Hill
4. Chandrakasan AP, Brodersen RW (1995) Low power digital CMOS design. Kluwer Academic Publishers, Boston
5. Fujita T, Hatori F (2015) A comprehensive study on power reduction techniques in deep submicron technologies. Int J Eng Res Appl: 517–521