Author:
Duari Chusen,Birla Shilpi
Reference13 articles.
1. Zhang K-J, Chen K, Pan W-T, Ma P-J (2010) A research of dual-port SRAM cell using 8T. In: 2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT). IEEE, pp 2040–2042
2. Wen L, Li Z, Li Y (2013) Single-ended, robust 8T SRAM cell for low-voltage operation. Microelectron J 44(8):718–728
3. Razavipour G, Afzali-Kusha A, Pedram M (2009) Design and analysis of two low-power SRAM cell structures. IEEE Trans Very Large Scale Integr (VLSI) Syst 17(10):1551–1555
4. Nii K, Makino H, Tujihashi Y, Morishima C, Hayakawa Y, Nunogami H, Arakawa T, Hamano H (1998) A low power SRAM using auto-backgate-controlled MT-CMOS. In: Proceedings of 1998 international symposium on low power electronics and design. IEEE, pp 293–298
5. Kim, T-H, Liu J, Keane J, Kim CH (2007) A high-density subthreshold SRAM with data-independent bitline leakage and virtual ground replica scheme. In: 2007 IEEE International Solid-State Circuits Conference, ISSCC 2007. Digest of Technical Papers. IEEE, pp 330–606
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