Cluster based MPSoC architecture: an on-chip message passing implementation-Reference-Cited by-同舟云学术

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Cluster based MPSoC architecture: an on-chip message passing implementation

Published:2013-09 Issue:3-4 Volume:17 Page:587-607
ISSN:0929-5585
Container-title:Design Automation for Embedded Systems
language:en
Short-container-title:Des Autom Embed Syst

Author:

Brillu Romain,Pillement Sébastien,Lemonnier Fabrice,Millet Philippe

Publisher

Springer Science and Business Media LLC

Subject

Hardware and Architecture,Software

Link

http://link.springer.com/content/pdf/10.1007/s10617-014-9146-5.pdf

Reference24 articles.

1. Kumar R, Tullsen DM, Jouppi NP (2006) Core architecture optimization for heterogeneous chip multiprocessors. In: Parallel architectures and compilation techniques, pp 23–32

2. Jantsch A, Chen X, Naeem A, Zhang Y, Penolazzi S, Lu Z (2012) Memory architecture and management in an NoC platform. In: Scalable multi-core architectures. Springer, pp 3–31

3. Casu MR, Roch MR, Tota SV, Zamboni M (2011) A NoC-based hybrid message-passing/shared-memory approach to CMP design. Microprocess Microsyst 35(2):261–273

4. Marchesan Almeida G, Sassatelli G, Benoit P, Saint-Jean N, Varyani S, Torres L, Robert M (2009) An adaptive message passing MPSoC framework. Int J Reconfigurable Comput

5. Benini L, Flamand E, Fuin D, Melpignano D (2012) P2012: building an ecosystem for a scalable, modular and high-efficiency embedded computing accelerator. In: Design, automation and test in Europe (DATE), pp 983–987

Cited by 1 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. System management recovery in NoC-based many-core systems;Analog Integrated Circuits and Signal Processing;2020-03-12

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