Author:
Casu Mario R.,Roch Massimo Ruo,Tota Sergio V.,Zamboni Maurizio
Subject
Artificial Intelligence,Computer Networks and Communications,Hardware and Architecture,Software
Reference35 articles.
1. ARM Cortex A9 MPCoreTM processors, white paper .
2. J.L. Shin et al., A 40nm 16-core 128-thread CMT SPARC SoC processor, in: Proceedings of the 2010 IEEE International Solid-State Circuits Conference, San Jose (CA), February 2010, pp. 98–99.
3. J.G. Davis et al., Maximizing CMP throughput with mediocre cores, in: Proceedings of the 14th International Conference on Parallel Architectures and Compilation Techniques (PACT’05), Saint Louis, Missouri, September 19, 2005, pp. 51–62.
4. S. Vangal et al., An 80-tile 1.2 TFLOPS network-on-chip in 65nm CMOS, in: Proceedings of the 2007 IEEE International Solid-State Circuits Conference, San Jose (CA), February 2007, pp. 5–6.
5. J. Howard et al., A 48-core IA-32 message-passing processor with DVFS in 45nm CMOS, in: Proceedings of the 2010 IEEE International Solid-State Circuits Conference, San Jose (CA), February 2010, pp. 108–109.
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