On local transformations and path delay fault testability-Reference-Cited by-同舟云学术

On local transformations and path delay fault testability

Published:1995-12 Issue:3 Volume:7 Page:173-191
ISSN:0923-8174
Container-title:Journal of Electronic Testing
language:en
Short-container-title:J Electron Test

Author:

Hengster Harry,Drechsler Rolf,Becker Bernd

Publisher

Springer Science and Business Media LLC

Subject

Electrical and Electronic Engineering

Link

http://link.springer.com/content/pdf/10.1007/BF00995312.pdf

Reference33 articles.

1. M. Abramovici, M.A. Breuer, and A.D. Friedman,Digital Systems Testing and Testable Design, Computer Science Press, New York, 1990.

2. R.L. Wadsack, ?Fault Modeling and Logic Simulation of CMOS and MOS Integrated Circuits,?Bell System Technical Jour., 57, 1978.

3. G.L. Smith, ?Model for Delay Faults Based Upon Paths,?Proc. of Int'l Test Conf., 1985, pp. 342?349.

4. E. Lindbloom, J.A. Waicukauski, B. Rosen, and V. Iyengar, ?Transition Fault Simulation by Parallel Pattern Single Fault Propagation,?Proc. of Int'l Test Conf., 1986, pp. 542?549.

5. S.M. Reddy, C.J. Lin, and S. Patil, ?An Automatic Test Pattern Generator for the Detection of Path Delay Faults,?Proc. of Int'l Conf. on CAD, 1987, pp. 284?287.

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