LOT: Logic Optimization with Testability. New transformations for logic synthesis-Reference-Cited by-同舟云学术

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LOT: Logic Optimization with Testability. New transformations for logic synthesis

Published:1998-05 Issue:5 Volume:17 Page:386-399
ISSN:0278-0070
Container-title:IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
language:
Short-container-title:IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

Author:

Chatterjee M.,Pradhan D.K.,Kunz W.

Publisher

Institute of Electrical and Electronics Engineers (IEEE)

Subject

Electrical and Electronic Engineering,Computer Graphics and Computer-Aided Design,Software

Link

http://xplorestaging.ieee.org/ielx4/43/15209/00703921.pdf?arnumber=703921

Cited by 7 articles. 订阅此论文施引文献订阅此论文施引文献，注册后可以免费订阅5篇论文的施引文献，订阅后可以查看论文全部施引文献

1. Finding Multiple Equivalence-Preserving Transformations in Combinational Circuits through Incremental-SAT;Journal of Electronic Testing;2010-01-30

2. Exploiting incrementality in SAT-based search for multiple equivalence-preserving transformations in combinational circuits;2009 IEEE International High Level Design Validation and Test Workshop;2009-11

3. Power optimization of Sequential Circuits by Retiming and Rewiring;2006 49th IEEE International Midwest Symposium on Circuits and Systems;2006-08

4. A BIST pattern generator design for near-perfect fault coverage;IEEE Transactions on Computers;2003-12

5. Logic insertion to speed-up logic verification: a recent development;Proceedings Seventh International On-Line Testing Workshop

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