A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs-Reference-Cited by-同舟云学术

A charge transfer-based high performance, ultra-low power CMOS charge pump for PLLs

Published:2016-09-02 Issue:3 Volume:89 Page:561-573
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Schober Susan Marya,Choma John

Funder

MOSIS

Defense Sciences Office, DARPA

National Science Foundation

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-016-0829-7.pdf

Reference17 articles.

1. Rhee, W. (1999, July). Design of high-performance CMOS charge pumps in phase-locked loops. In Circuits and Systems, 1999. ISCAS’99. Proceedings of the 1999 IEEE International Symposium on (Vol. 2, pp. 545–548). IEEE.

2. Floyd, M. G. (1980). Charge-pump phase-lock loops. IEEE Transaction on communications, 28(11), 1849–1858.

3. Shi, X., Imfeld, K., Tanner, S., Ansorge, M., & Farine, P. A. (2006). A low-jitter and low-power CMOS PLL for clock multiplication. In Solid-State Circuits Conference, 2006. ESSCIRC 2006. Proceedings of the 32nd European (pp. 174–177). IEEE.

4. Charles, C. T., & Allstot, D. J. (2008, May). A buffered charge pump with zero charge sharing. In 2008 IEEE International Symposium on Circuits and Systems, ISCAS 2008. Seattle, WA.

5. Rategh, H. R., Samavati, H., & Lee, T. H. (2000). A CMOS frequency synthesizer with an injection-locked frequency divider for a 5-GHz wireless LAN receiver. IEEE Journal of Solid-State Circuits, 35(5), 780–787.

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