Resilient design of current steering DACs using a transistor level approach-Reference-Cited by-同舟云学术

Resilient design of current steering DACs using a transistor level approach

Published:2016-09-15 Issue:1 Volume:90 Page:29-41
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Mirzaie Nahid,Shamsi Hossein,Byun Gyung-Su

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-016-0859-1.pdf

Reference42 articles.

1. Sahoo, B., & Razavi, B. (2013). A 10-b 1-GHz 33-mW CMOS ADC. IEEE Journal Solid-State Circuits, 48(6), 2366–2380.

2. Mafi, H., Yavari, M., & Shamsi, H. (2016). Digital calibration of DAC unit elements mismatch in pipelined ADCs. IEEE Trans Circuits and Systems I: Regular Papers, 63(1), 34–45.

3. Mirzaie, N., Shamsi, H., & Byun, G. S. (2017). Automatic design and yield enhancement of data converters. Journal of Circuits, Systems and Computers. doi: 10.1142/S0218126617500189 .

4. Blish, R., et al. (2003). Critical reliability challenges for the international technology roadmap for semiconductors (ITRS). Technology Transfer.

5. Gielen, G., et al. (2008). Emerging yield and reliability challenges in nanometer CMOS technologies. In Proc. design, automation and test in Europe (pp. 1322–1327).

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