Author:
Sivakumar P.,Pandiaraj K.,JeyaPrakash K.
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Reference27 articles.
1. Das, S. S., & Bose, R. (2013). A genetic algorithm based approach for optimization of test time and TAM length For 3D SoC considering pre-bond test under the constraint on the number of TSVs. International Journal of Engineering Research and Applications (IJERA), 3, 347–356.
2. Pandiaraj K., et al. (2017). Minimizationof wirelength in 3d IC routing by using differential evolution algorithm. In 2017 IEEE international conference on electrical, instrumentation and communication engineering (ICEICE) (pp. 1–5).
3. Pandiaraj, K et al. (2017). Reduction of temperature rise in 3D IC routing. In 2017 IEEE international conference on electrical, instrumentation and communication engineering (ICEICE) (pp. 1–5).
4. Osmolovskyi, S. et al. (2018). Optimal die placement for interposer-based 3D ICs. In Proceedings of the 23rd Asia and South Pacific design automation conference (pp. 513–520).
5. Hou, L., et al. (2018). A method to alleviate hot spot problem in 3D IC. Microelectronic Engineering,190, 19–27.
Cited by
13 articles.
订阅此论文施引文献
订阅此论文施引文献,注册后可以免费订阅5篇论文的施引文献,订阅后可以查看论文全部施引文献