Variability aware SVM macromodel based design centering of analog circuits-Reference-Cited by-同舟云学术

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Variability aware SVM macromodel based design centering of analog circuits

Published:2011-10-15 Issue:1 Volume:73 Page:77-87
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Boolchandani D.,Garg Lokesh,Khandelwal Sapna,Sahula Vineet

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-011-9799-y.pdf

Reference27 articles.

1. Mukherjee, T., Carley, L. R., & Rutenbar, R. (2000). Efficient handling of operating range and manufacturing line variations in analog cell synthesis. IEEE Transactions on Computer-Aided Design, 19, 825–839.

2. Kurker, C. M., Paulos, J. J., Gyurcsik, R. S., & Lu, J.-C. (1993). Hierarchical yield estimation of large analog integrated circuits. IEEE Journal of Solid-State Circuits, 28, 203–209.

3. Kiely, T., & Gielen, G. G. E. (2004). Performance modeling of analog integrated circuits using least-squares support vector machines. In Proceedings of DATE (pp. 448–453).

4. Ding, M., & Vemuri, R. (2005). A combined feasibility and performance macromodel for analog circuits. In Proceedings of IEEE design automation conference (pp. 63–68).

5. Barros, J. G., & Horta, N. (2007). Nuno Ga-SVM feasibility model and optimization kernel applied to analog ICs design automation. In Proceedings of 17th ACM great lake symposium on VLSI, USA (pp. 469–472).

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1. Variability aware transistor stack based regression surrogate models for accurate and efficient statistical leakage estimation;Microelectronics Journal;2017-11

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