Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design-Reference-Cited by-同舟云学术

Optimizing Drain Current, Inversion Level, and Channel Length in Analog CMOS Design

Published:2006-03-10 Issue:2 Volume:47 Page:137-163
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Binkley D. M.,Blalock B. J.,Rochelle J. M.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-006-2949-y.pdf

Reference171 articles.

1. G.E. Gielen, and R.A. Rutenbar, “Computer-aided design of analog and mixed-signal integrated circuits.” Proceedings of the IEEE, vol. 88 no. 12, pp. 1825–1854, 2000.

2. B. Martin, “Automation comes to analog.” IEEE Spectrum, pp. 70–75, 2001.

3. Barcelona Design, Inc., http://www.barcelonadesign.com.

4. Neolinear, Inc., now part of Cadence Design Systems, http://www.cadence.com.

5. R. Schwencker, F. Schenkel, M. Pronath, and H. Graeb, “Analog circuit sizing using adaptive worst-case parameters sets.” In Proceedings of the 2002 Design and Test in Europe Conference, pp. 581–585, 2002.

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