Design and Analysis of CMOS Analog Circuit in Systematic Method on 130nm-Reference-Cited by-同舟云学术

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Design and Analysis of CMOS Analog Circuit in Systematic Method on 130nm

Published:2022-12-02 Issue: Volume: Page:
ISSN:
Container-title:2022 IEEE 2nd International Conference on Mobile Networks and Wireless Communications (ICMNWC)
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Author:

Vadaboyina Appala Raju¹,Gedela Indira Devi²,Bobbili V Rama Gowri³,Guduri Soundarya⁴,Gubbala Arshini⁵

Affiliation:

1. Vignan Institute of Information Technology(Autonomous),Electronics and Communication Engineering,Visakhapatnam,India

2. Anil Neerukonda Institute of Technology & Sciences,Electronics and Communication Engineering,Visakhapatnam,India

3. Electronis and Communication Engineering GVP college of engineering for women,Visakhapatnam,India

4. Gandi Institute of Technology and Mangement,Electronics and Communication Engineering,Visakhapatnam,India

5. Vignan Institute of Information Technology,Electronics and Communication Engineering,Visakhapatnam,India

Publisher

IEEE

Link

http://xplorestaging.ieee.org/ielx7/10031272/10031281/10031862.pdf?arnumber=10031862

Reference25 articles.

1. Graphical Representations for Analog IC Design in Deep and Ultra-Deep Submicron CMOS;manolov;Annual Journal of Electronics,2015

2. Design Automation of 5-T OTA using gm/ID methodology

3. 1.3 Analog CMOS from 5 micrometer to 5 nanometer

4. Design and optimisation of a cascode low noise amplifier (LNA) using MOST scattering parameters and gm/ID ratio;castagnola;2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS),2018

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