A 98.1 % CE, 100 mA MLC multi-reference output all digital LDO with fast settling and digital self calibration for DVFS and multi-VDD applications-Reference-Cited by-同舟云学术

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A 98.1 % CE, 100 mA MLC multi-reference output all digital LDO with fast settling and digital self calibration for DVFS and multi-VDD applications

Published:2016-09-06 Issue:2 Volume:89 Page:437-450
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Kaedi S.,Ghaznavi-Ghoushchi M. B.,Rahimi M.

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-016-0843-9.pdf

Reference21 articles.

1. Vaisband, I., et al. (2015). Distributed LDO regulators in a 28 nm power delivery system. Analog Integrated Circuits and Signal Processing, 83(3), 295–309.

2. Otsuga et al. (2012) “An On-Chip 250 mA 40 nm CMOS digital LDO using dynamic sampling clock frequency scaling with offset-free TDC-based voltage.” In Proceedings of the IEEE International SOC Conference (pp. 11–14).

3. Giustolisi, G. Palumbo, and Spitale E.(2008) “Low-voltage LDO compensation strategy based on current amplifiers,” In Proceedings IEEE International Symposium on Circuits Systems (ISCAS) (pp. 2681–2684).

4. Onouchi et al. (2011) “A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process,” In Proceedings of the Asian Solid-State Circuits Conference. (A-SSCC) (pp. 37–40).

5. Kose, S., et al. (2013). Active filter-based hybrid on-chip DC–DC converter for point-of-load voltage regulation. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 21(4), 680–691.

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