A new approach to sizing analog CMOS building blocks using pre-compiled neural network models-Reference-Cited by-同舟云学术

A new approach to sizing analog CMOS building blocks using pre-compiled neural network models

Published:2011-05-10 Issue:3 Volume:70 Page:265-281
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Mendhurwar Kaustubha,Sundani Harsh,Aggarwal Priyanka,Raut Rabin,Devabhaktuni Vijay

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-011-9648-z.pdf

Reference56 articles.

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3. Cohn, J. M., Garrod, D. J., Rutenbar, R. A., & Carley, R. (1994). Analog device-level layout automation. New York, NY: Springer.

4. Gajski, D. D., Dutt, N. D., & Pangrale, B. M. (1986). Silicon compilation (tutorial). In IEEE Proceedings of CICC (pp. 102–110). Rochester, NY, May 1986.

5. Massara, R. E., Nadiadi, Y., & Winder, G. L. (1989). Silicon compilation in analog and digital custom VLSI design. In Progress in computer aided VLSI design (pp. 91–135). Ablex: New York, NY.

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