A low-power low-jitter DLL with a differential closed-loop duty cycle corrector
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/article/10.1007/s10470-017-0984-5/fulltext.html
Reference33 articles.
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3. Hatakeyama, A., et al. (1997). A 256-Mb SDRAM using a register-controlled digital DLL. IEEE Journal of Solid-State Circuits, 32(11), 1728–1734.
4. Jeon, Y., et al. (2004). A 66-333-MHz 12-mW register-controlled DLL with a single delay line and adaptive-duty-cycle dividers for production DDR SDRAMs. IEEE Journal of Solid-State Circuits, 39(11), 2087–2092.
5. Jung, I., et al. (2008). A 0.004 mm portable multiphase clock generator tile for 1.2 GHz RISC microprocessor. IEEE Transaction Circuits System II, Express Briefs, 55(2), 116–120.
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