A 6-bit hierarchal TDC architecture for time-based ADCs
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-020-01734-6.pdf
Reference21 articles.
1. Mhiri, M., Saad, S., Hammadi, A. B., & Besbes, K. (2017). A new hybrid TDC based on GRO-pseudo delay architecture with fractional code and wide time range detection for divider-less ADPLL. Analog Integrated Circuits and Signal Processing, 93(2), 265–275.
2. Mhiri, M., Saad, S., Ben Hammadi, A., et al. (2017). A new hybrid TDC based on GRO-pseudo delay architecture with fractional code and wide time range detection for divider-less ADPLL. Analog Integrated Circuits and Signal Processing, 93, 265–275.
3. Xu, Y., Wu, G., Belostotski, L., & Haslett, J. W. (2016). 5-bit 5-GS/s non-interleaved time-based ADC in 65-nm CMOS for radio-astronomy applications. IEEE Transactions on Very Large-Scale Integration (VLSI), 24(12), 3513–3525.
4. Lin, Y.-C., & Tsao, H.-W. (2020). A 5-bit 400-MS/s time domain flash ADC in 0.18-μm CMOS. Analog Integrated Circuits Signal Process Journal, 102, 369–378.
5. Rashdan, M., Haslett, J., & Maundy, B. (2012). Multiple-valued time-based architecture for serial communication links. In The 42th IEEE international symposium on multiple-valued logic (ISMVL), Victoria, BC, Canada, 14–16 May. 2012, (pp. 1–6).
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