CMOS substrate coupling modeling and analysis flow for submicron SoC design
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-016-0883-1.pdf
Reference22 articles.
1. Muhtaroglou, A., et al. (2004). On-die droop detector for analog sensing of power supply noise. IEEE Journal of Solid State Circuits, 39(4), 651–660.
2. Felder, M., & Ganger, J. (1999). Analysis of ground-bounce induced substrate noise coupling in a low resistive bulk epitaxial process: Design strategies to minimize noise effects on a mixed signal chip. IEEE Transaction on Circuits and Systems II, 46(11), 1427–1436.
3. Charbon, E., et al. (1999). Modeling digital substrate noise injection in mixed signal IC’s. IEEE Transactions on Computer Aided Design, 18(3), 301–310.
4. Gharpurey, R., & Meyer, G. (1996). Modeling and analysis of substrate coupling in integrated circuits. IEEE Journal of Solid state circuits, 31(3), 125–128.
5. Stanisic, B. R., et al. (1994). Addressing substrate coupling in mixed-mode IC’s: Simulation and power distribution synthesis. IEEE Journal of Solid state circuits, 29(3), 226–238.
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