Low power self-controllable voltage level and low swing logic based 11T SRAM cell for high speed CMOS circuits
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-018-1277-3.pdf
Reference27 articles.
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3. Gavaskar, K., & Priya, S. (2013). Design of efficient low power stable 4-bit memory cell. International Journal of Computer Applications, 84(1), 0975–8887.
4. Gavaskar, K., Ragupathy, U. S. (2014). An efficient design and comparative analysis of low power memory cell structures. In IEEE international conference on green computing, communication and electrical engineering (ICGCCEE’14) (pp. 489–493).
5. Borkar, S. (1999). Design challenges of technology scaling. IEEE Micro, 19(4), 23.
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