Efficient optimization of integrated spiral inductor with bounding of layout design parameters
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
http://link.springer.com/content/pdf/10.1007/s10470-007-9061-9.pdf
Reference20 articles.
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2. Abidi, A. A. (2004). RF CMOS comes of age. IEEE Journal of Solid-State Circuits, 39, 549–561.
3. Burghartz, J. N. (2001). Status and trends of silicon RF technology. Microelectronics Reliability, 41, 13–19.
4. Long, J. R., & Copeland, M. A. (1997). The modeling, characterization, and design of monolithic inductors for silicon RF IC’s. IEEE Journal of Solid-State Circuits, 32, 357–369.
5. Koutsoyannopoulos, Y. K., & Papananos, Y. (2000). Systematic analysis and modeling of integrated inductors and transformers in RF IC design. IEEE Transactions on Circuits and Systems-II: Analog and Digital Signal Processing, 47, 699–713.
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2. Design of a multilayer on-chip inductor by computational electromagnetic modelling;Journal of Electrical Engineering;2019-09-01
3. Layout optimization of planar inductors for high-efficiency integrated power converters;Analog Integrated Circuits and Signal Processing;2019-07-08
4. Novel on-chip spiral inductors with back hollow structure;Modern Physics Letters B;2017-01-10
5. Optimization of Spiral Inductor with Bounding of Layout Parameters;Design and Analysis of Spiral Inductors;2013-09-07
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