Design of a multilayer on-chip inductor by computational electromagnetic modelling-Reference-Cited by-同舟云学术

Design of a multilayer on-chip inductor by computational electromagnetic modelling

Published:2019-09-01 Issue:5 Volume:70 Page:379-385
ISSN:1339-309X
Container-title:Journal of Electrical Engineering
language:en
Short-container-title:

Author:

Dhamodaran Muneeswaran¹,Jegadeesan Subramani¹,Murugan Arunachalam¹

Affiliation:

1. Department of Electronics and Communication Engineering , M. Kumarasamy College of Engineering , Karur , Tamil Nadu, 639113 , India

Abstract

Abstract This paper presents a design of typical multilayer on-chip inductor to determine the layout parameters of the desired inductance value of electromagnetic modeling. The inductance and quality factor of multilayer on-chip spiral inductors are determined by its layout parameters and technological parameters. These layout parameters must be optimized to obtain the maximum quality factor at the desired frequency of operation. An electromagnetic model with fewer assumptions than empirical equations and higher efficiency than full-field solvers would be welcome. So would facile comparisons of different inductor structures. This paper describes recent works on the electromagnetic modeling of on-chip inductor structures applied to the comparison of inductor geometries, including the traditional spiral inductor and a novel multilayer inductor. The electromagnetic modeling of the investigative model is presented. The modeling and simulation are implemented using the method of moments. To simulate the proposed algorithm, the EM Simulator software is used.

Publisher

Walter de Gruyter GmbH

Link

https://www.sciendo.com/pdf/10.2478/jee-2019-0069

Reference16 articles.

1. [1] G. Haobijam and R. Paily, “Efficient Optimization of Integrated Spiral Inductor with Bounding of Layout Design Parameters”, Analog Integrated Circuits Signal Processing, vol. 51, no. 3, pp. 131–140, 2007.10.1007/s10470-007-9061-9

2. [2] B. V. N. S. M. N. Deevi and N. B. Rao, “Multi-Layer On-Chip Inductor for 10–100 GHz Frequency Applications”, Electronics Letters, vol. 51, no. 3, pp. 270–272, 2015.10.1049/el.2014.3202

3. [3] S. J. Pan, L. W. Li, and W. Y. Yin, “Performance Trends of On-Chip Spiral Inductors for RFICs”, Progress Electromagnetics Research PIER, vol, 45, pp. 123–151, 2004.10.2528/PIER03062303

4. [4] M. Dhamodaran, R. Praveen Kumar and S. Jegadeesan, “On-Chip Spiral Inductors On-Chip Spiral Transistors for Accurate Numerical Modeling”, Journal of Magnetics, vol. 23, no. 1, pp. 50–54, 2018.10.4283/JMAG.2018.23.1.050

5. [5] C. P. Yue and S. S. Wong, “On-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF ICs”, IEEE Journal of Solid-State Circuits, vol. 33, no. 5, pp. 743–752, 1998.10.1109/4.668989

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