A dual-residue pipelined SAR ADC using only zero-crossing signals
Author:
Publisher
Springer Science and Business Media LLC
Subject
Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing
Link
https://link.springer.com/content/pdf/10.1007/s10470-021-01860-9.pdf
Reference23 articles.
1. Hurrell, C. P., Lyden, C., Laing, D., Hummerston, D., & Vickery, M. (2010). An 18b 12.5 MS/s ADC with 93 dB SNR. IEEE Journal of Solid-State Circuits, 45(12), 2647–2654
2. Lee, C. C., & Flynn, M. P. (2011). A SAR-assisted two-stage pipeline ADC. IEEE Journal of Solid-State Circuits, 46(4), 859–869
3. Verbruggen, B., Iriguchi, M., & Craninckx, J. (2012). A 1.7 mW 11b 250 MS/s 2-times interleaved fully dynamic pipelined SAR ADC in 40 nm digital CMOS. IEEE Journal of Solid-State Circuits, 47(12), 2880–2887
4. Zhou, Y., & Chiu, Y. (2015). Digital calibration of inter-stage nonlinear errors in pipelined SAR ADCs. Analog Integrated Circuits and Signal Processing, 82, 533–542
5. Kuppambatti, J., & Kinget, P. R. (2014). Current reference pre-charging techniques for low-power zero-crossing pipeline-SAR ADCs. IEEE Journal of Solid-State Circuits, 49(3), 683–694
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1. A 12-Bit 260-MS/s Pipelined-SAR ADC With Ring-TDC-Based Fine Quantizer for Automatic Cross-Domain Scale Alignment;IEEE Journal of Solid-State Circuits;2023-10
2. A Bi/Tri-level Self-Adaptive Two-Step DAC Switching Scheme for High-Power Efficiency SAR-Based ADCs;Circuits, Systems, and Signal Processing;2023-03-29
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