Digital calibration of inter-stage nonlinear errors in pipelined SAR ADCs-Reference-Cited by-同舟云学术

Digital calibration of inter-stage nonlinear errors in pipelined SAR ADCs

Published:2015-01-30 Issue:3 Volume:82 Page:533-542
ISSN:0925-1030
Container-title:Analog Integrated Circuits and Signal Processing
language:en
Short-container-title:Analog Integr Circ Sig Process

Author:

Zhou Yuan,Chiu Yun

Publisher

Springer Science and Business Media LLC

Subject

Surfaces, Coatings and Films,Hardware and Architecture,Signal Processing

Link

http://link.springer.com/content/pdf/10.1007/s10470-015-0493-3.pdf

Reference12 articles.

1. Liu, W, Huang, P., & Chiu, Y., (2010). A 12b 22.5/45MS/s 3.0 mW 0.059 mm2 CMOS SAR ADC achieving over 90 dB SFDR. In IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers (pp. 380–381).

2. Lee, C. C., & Flynn, M. P. (2011). A SAR-assisted two-stage pipeline ADC. IEEE Journal of Solid-State Circuits, 46(4), 859–869.

3. Furuta, M, Nozawa, M., & Itakura, T. (2010). A 0.06 mm2 8.9b ENOB 40MS/s pipelined SAR ADC in 65 nm CMOS. In IEEE International Solid-State Circuits Conference (ISSCC), Digest of Technical Papers (pp. 382–383).

4. Chiu, Y., Tsang, C. W., Nikolic, B., & Gray, P. R. (2004). Least mean square adaptive digital background calibration of pipelined analog-to-digital converters. IEEE Transactions on Circuits and Systems—Part I, 51(1), 38–46.

5. McNeill, J., Coln, M. C. W., & Larivee, B. J. (2005). Split ADC architecture for deterministic digital background calibration of a 16-bit 1-MS/s ADC. IEEE Journal of Solid-State Circuits, 40(12), 2437–2445.

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